Flash memory devices have developed into a popular source of non-volatile memory for a wide range of electronic applications. Flash memory devices typically use a one-transistor memory cell that allows for high memory densities, high reliability, and low power consumption. Common uses for flash memory include personal computers, personal digital assistants (PDAs), digital cameras, and cellular telephones. Program code and system data such as a basic input/output system (BIOS) are typically stored in flash memory devices for use in personal computer systems.
Non-volatile memory cells are read during a sense operation using sense circuitry (e.g., sense amplifiers). Bit lines are coupled to the sense circuitry that detects the state of a target memory cell by sensing voltage or current on a particular bit line. A typical sense operation includes precharging, to a particular voltage level (e.g., 0.5V), the bit lines coupled to memory cells selected to be read.
During a typical sense operation of a memory block, alternate bit lines coupled to NAND strings of memory cells are read. In other words, an initial sense operation might read the odd bit lines of memory cells while a subsequent sense operation would read the even bit lines of memory cells. Using this alternate bit line procedure, no two adjacent bit lines are read simultaneously. The bit lines that are not being read are typically grounded to provide shielding between bit lines that are being read. This reduces the bit line-to-bit line coupling that can occur as a result of the voltage level on the bit lines changing between sensing.
Since only alternate bit lines of memory cells are read during a sense operation, reading a memory block can take twice as long as reading all of the bit lines simultaneously. One way that has been proposed to decrease the read time of a non-volatile memory device is to read all of the bit lines substantially simultaneously (i.e., an all bit line read (ABL)) using a multi-step sense operation that can reduce the bit line-to-bit line coupling. This is accomplished by measuring the cell current on the bit line by estimating the residual charge remaining on a capacitor coupled to the bit line after a sampling time has elapsed.
FIG. 1 illustrates a timing diagram of a typical prior art multi-step sense operation. This timing diagram shows three different 101-103 sense operations.
The lower waveform 105 shows the sensing trigger signal that signals the beginning of each sense cycle. Each time the sense trigger signal goes from low to high, a new sense operation is performed.
The middle waveform 107 shows the residual charge remaining TDC on the capacitor coupled to the bit line. It can be seen that as one sense operation ends, the capacitor discharges so that TDC starts to go to 0V until the next sense trigger signal causes the capacitor to recharge.
The top waveform 109 shows the bit line voltage for a bit line being read. This waveform also shows the bit line-to-bit line coupling 110, 111 that occurs due to a change in voltage on adjacent bit lines. Before this bit line can be sensed by the sense amplifier, the bit line voltage has to recover to the bit line bias level. Waiting for this recovery period results in a read delay during which the sense amplifiers cannot perform a sense operation.
For the reasons stated above, and for other reasons stated below that will become apparent to those skilled in the art upon reading and understanding the present specification, there is a need in the art to decrease the read time of a memory device.